Samsung Electronics Joins Transition to 12-inch Large Masks... Aiming to Secure High-NA Process Productivity

Samsung Electronics is participating in a development consortium with ASML to transition existing 6-inch photomasks to 12-inch class large masks. This is because as semiconductor circuits become finer, changing the specifications of the mask, which is the original of the circuit, is emerging as an essential task.

The 'Half Field' limitations of High-NA EUV where exposure area is halved

According to the Impossible Engineering - New IT Technologies video, the next-generation exposure equipment, High-NA EUV, has a numerical aperture (NA) of 0.55, which is higher than the existing EUV (NA 0.33). While this allows for the implementation of patterns approximately 1.7 times smaller than existing equipment, it also brings physical constraints. In the process of gathering light at a wider angle, reflection problems of light hitting the mask occur, and to solve this, an 'Anamorphic' optical method was adopted, which reduces one direction by one-fourth and the other direction by one-eighth.

While this method allows for more detailed circuit printing, it reduces the area that can be printed in a single exposure (reticle limit) from the existing 858㎟ to exactly about half, 429㎟. The video explains this phenomenon as the 'Half Field' problem. Large GPU chips such as NVIDIA's A100 (826㎟) or H100 (814㎟) are close to the size that can be printed at once with existing EUV, but if High-NA is applied, a 'Stitching' process is required to print the chip in two sections and then join the boundaries.

The stitching process requires precise nanometer-scale positioning, and there is a risk of wiring defects if light excessively overlaps or is insufficient at the boundary areas. To prevent this, the burden on the process increases, such as widening the spacing between wires near the boundary during the design stage. In fact, according to ASML's equipment conditions, there is a productivity degradation issue where equipment (EXE:5200B) that can process 175 wafers per hour when not using stitching sees its throughput decrease to 135 wafers when using stitching.

Samsung Electronics and SK hynix's memory-centered strategy and TSMC's foundry calculations

Samsung Electronics has set a goal to apply High-NA EUV to advanced DRAM mass production for the first time in the memory industry in 2028. In the memory field, since the chip size is relatively smaller than a GPU, there is an advantage that the process can be done without stitching even within the reduced exposure area of High-NA. Memory companies expect the effect of removing 'Multi-Patterning', which simplifies complex manufacturing processes, through High-NA. Citing ASML's announcement, the video mentioned the possibility that a task requiring 3 masks with existing 0.33 NA EUV for a specific pattern could be handled with 1 mask using High-NA.

SK hynix is also preparing for High-NA with the goal of DRAM mass production in 2028. SK hynix has already announced that it installed ASML's mass-production High-NA equipment, EXE:5200B, at the M16 Fab in September 2025. However, the 'first in the memory industry' targeted by Samsung Electronics refers to the application to product mass production, and since the 'first' mentioned by SK hynix concerns equipment installation, the target timing for both companies is analyzed to be the same year, 2028.

On the other hand, the strategy of TSMC, which holds a 72.5% foundry market share (as of Q2 2024), is different. Since TSMC must implement the designs of large AI chip customers such as NVIDIA exactly as they are, it strictly calculates the Half Field problem and cost-efficiency that occurs when printing massive chips. TSMC judged that High-NA is not absolutely necessary for the A16 process in 2024 and plans to use High-NA for mass production in advanced processes starting from 2030. TSMC is also participating in the transition to 12-inch large masks and envisions preparing a full exposure system using new masks by 2033.

Productivity innovation and future outlook brought by 12-inch large masks

The development of 12-inch class large masks in which Samsung Electronics is participating is a move to fundamentally solve the aforementioned 'Stitching' burden. If the original area is widened through specifications such as 6x12-inch, which extends the existing 6-inch mask long in one direction, large chips can be printed at once in High-NA without stitching. ASML explained that if the transition to large masks is successful, the productivity of the High-NA system can be increased by up to 40%.

Currently, Intel is accumulating data by deploying High-NA into actual product mass production the fastest. Intel stated that as of September 2026, the number of wafers processed through High-NA has exceeded 1 million, and the yield is also at a similar level to existing EUV. Ultimately, the industry observation is that the core of the High-NA competition is not simply about who introduces the equipment first, but about which chip to apply which layer to lower manufacturing costs and reduce process steps.