SK hynix Strengthens Next-Generation AI Memory Cooperation with TSMC, Wins Partner of the Year Award for Second Consecutive Year

SK hynix has materialized its next-generation memory technology roadmap by joining hands with TSMC, a key partner in the AI semiconductor ecosystem. From High Bandwidth Memory (HBM) to maximize AI computing performance to next-generation SSDs, which are core to data storage, the company emphasized its technological leadership by presenting a product lineup covering the entire AI infrastructure.

SK hynix announced that it participated in the 'TSMC Open Innovation Platform (OIP) Conference' held in Santa Clara, California, USA, on the 23rd (local time). At this conference, SK hynix used the slogan 'The Memory behind the Intelligence at Scale' and unveiled a large number of next-generation memory solutions to be installed in AI accelerators and servers.

Unveiling HBM4 and SOCAMM2 to be installed in NVIDIA 'Vera Rubin'

The exhibition space was divided into an HBM layer to assist AI computing and a storage layer responsible for data storage. The HBM exhibition area, which interfaces with NVIDIA's next-generation superchip 'Vera Rubin', drew particular attention. Here, the 'HBM4 36GB 12-layer' product, which plays a role in reducing data transmission latency around the Rubin GPU cores, and the 'SOCAMM2 96GB', a low-power DRAM-based memory module that helps maintain the context of AI agents, were displayed as physical models.

In addition to HBM4, SK hynix demonstrated the evolution process of memory following AI technological advancements by gathering a high-performance HBM lineup including HBM4E 48GB 12-layer, HBM4 48GB 16-layer, and HBM3E 36GB 12-layer. Furthermore, it presented a product group optimized for the next-generation AI computing environment by also showcasing the 192GB model of SOCAMM2, which operates as the main system memory for AI servers.

From Server DRAM to Liquid-Cooling Supported SSDs... All-around Attack on AI Infrastructure

In the storage field, high-capacity and high-efficiency products designed to respond to the explosive increase in AI workloads drew attention. The server DRAM booth exhibited the industry's largest capacity '256GB 3DS RDIMM', the high-bandwidth '128GB MRDIMM', and the '64GB RDIMM' applying a 10nm-class 6th generation process.

In the SSD exhibition area, solutions to increase data center operational efficiency were emphasized. In particular, the 'PEB210 E1.S', which supports liquid cooling (DLC) methods, attracted high interest from data center customers. Additionally, the 'PS1101 E3.S', an eSSD developed by SK hynix for the first time based on QLC (Quadruples Level Cell), showed that the lineup targeting the next-generation storage market is being materialized, as inquiries from enterprise customers continue.

Results of HBM5 Verification Cooperation with TSMC... 'Partner of the Year Award' for 2 Consecutive Years

At this conference, SK hynix received the 'Partner of the Year Award' in the '3DFabric-HBM Integration' field from TSMC. This is the second consecutive year of receiving the award following last year. This is a result of recognizing the close cooperation shown by both companies in the process of verifying HBM5 based on TSMC's advanced packaging technology, CoWoS (Chip on Wafer on Substrate), to implement next-generation AI systems.

For HBM to implement performance, connection with advanced packaging technologies that combine it with GPUs and others is essential. SK hynix emphasized the importance of cooperation, stating, "We have been conducting verification together with TSMC from the early stages to lay the foundation for next-generation AI systems."

Meanwhile, Park Dae-sik, a team leader at SK hynix, who participated in a technical session, shared the changes in the PCIe (Peripheral Component Interconnect Express) interface and the next-generation SSD roadmap. Park stated, "As AI infrastructure expands, the PCIe-based eSSD market is expected to grow to 1,933EB by 2030," and "SK hynix is preparing next-generation SSD solutions based on chiplet technology to respond to 6th and 7th generation PCIe." Utilizing chiplet technology allows chips to be designed separately by function, enabling shorter development periods and power optimization.

Source: news.skhynix.co.kr