Intel Improves EMIB-T Substrate Yield to 45%... Emerging as an Alternative to TSMC CoWoS?

The substrate yield of Intel's advanced packaging technology, EMIB-T (Embedded Multi-die Interconnect Bridge-T), has recently risen to the 45% level, drawing attention as an alternative to diversify the AI chip packaging demand currently concentrated on TSMC's CoWoS (Chip on Wafer on Substrate). According to a video from 'Impossible Engineering - New IT Technologies', the EMIB-T substrate yield was at the 20–25% level in the second quarter of this year, but has recently improved to approximately 45%, with a goal of reaching 50% by the end of this September.

Differences in chip interconnection methods... EMIB-T has strengths in cost reduction and power supply

The core of AI accelerator production is packaging technology that connects GPUs and HBM (High Bandwidth Memory) with dense wiring. TSMC's CoWoS, which currently leads the market, is a method that uses a wide silicon plate (interposer). On the other hand, Intel's EMIB method is a structure that inserts a small silicon piece called a 'bridge' only in the sections where the chips meet. Intel explains that this allows for making only the parts requiring precise connections small, which can lower costs compared to methods using a wide interposer.

In particular, EMIB-T adds TSV (Through-Silicon Via) to the existing EMIB structure, securing not only data transmission between chips but also a path to supply power from the bottom to the top. This design is intended to solve the difficulties in power supply that arise as memory and computing chips grow larger and to reduce voltage fluctuations. Intel aims to increase manufacturing efficiency by mass-producing small bridges on wafers in advance and then embedding them into large package substrates.

Substrate yield is the deciding factor... Challenges in fine wiring and thermal deformation management

Improving yield is directly linked to expanding supply volume. According to the video, if the yield rises from 25% to 45%, it has the effect of increasing the amount of usable substrate by about 80% without expanding facilities. However, manufacturing process challenges remain before a stable supply can be provided to the volumes actually desired by customers. Substrate companies are experiencing high technical difficulty in the process of aligning fine wiring and integrating bridges containing TSV inside the substrate.

Specifically, when putting the bridge inside the substrate, the height must be accurately matched in addition to the horizontal and vertical positions. This is because the chip on top must be simultaneously connected to the fine contact points of the bridge and the contact points of the substrate. Additionally, since silicon and organic substrates have different expansion rates due to temperature changes, warping can occur during the assembly process or during use, and managing such thermal deformation is also cited as an important technical challenge. If defects are not filtered out at the substrate stage and are discovered after attaching expensive GPUs or HBM, the scale of loss becomes enormous, so securing substrate yield is an issue directly linked to cost reduction.

Logistics competitiveness using production bases in the United States... A clash with TSMC anticipated

For Intel's packaging technology to lead to actual orders, the customers' design and verification schedules must align with the substrate supply stabilization schedule. If Intel stabilizes its substrate yield and utilizes its production bases in the United States, it will possess strong competitiveness in terms of logistics. Unlike the current structure where chips produced at TSMC must be brought to Taiwan for packaging, Intel already possesses an advanced packaging production base in New Mexico, allowing it to offer an option to complete everything from chip manufacturing to packaging within the United States.

Of course, TSMC is also responding by building advanced packaging facilities in places like Arizona, United States. TSMC management has stated that packaging shortages limit customer growth, and expressed the position that even if another company takes on packaging, it is welcomed as an alternative since the demand for their own chips increases. Ultimately, whether Intel's EMIB-T can substantially take market share from TSMC depends on whether customers' AI chips are loaded with EMIB-T and shipped as scheduled, and whether the improved yield translates into actual supply volume.